Clock signals for dynamic reconfiguration of communication link bundles

ABSTRACT

In at least some embodiments, an electronic device includes a processor and a memory coupled to the processor. The electronic device also includes a serial communication link controller coupled to the processor, the serial communication link controller supporting dynamic reconfiguration of a plurality of communication link bundles. The serial communication link controller receives an input clock and generates first and second clock signals based on the input clock, the first and second clock signals having different clock rates and being provided to each of a plurality of communication link bundles.

BACKGROUND

Electronic devices (e.g., computers) have many different components thatcommunicate with each other. As technologies are developed, componentsand corresponding communication protocols evolve. Often, there is a needto support backwards compatibility between a previous generation ofcomponents/protocols and a next generation of components/protocols. Thisis because upgrading to the next generation components/protocols (orcorresponding devices) is expensive and may be unnecessary for manyconsumers. Thus, the upgrade process occurs over time and does notnecessarily involve all consumer products or components.

One example of a developing technology is the Peripheral ComponentInterconnect (PCI) Express architecture. PCI Express implements serialcommunication lanes to support high-speed communications betweendifferent computer components and/or peripherals, where the number ofserial communication lanes allocated to each component/peripheral canvary (e.g., 1×, 2×, 4×, 8×, 16× and so on). The PCI Express lanes fanout from an interconnect (i.e., a switch) that enables PCI Expresscomponents to communicate with each other and also that enables PCIExpress components to communicate with the host system. Differentinterconnects provide similar functionality as dictated by the PCIExpress specification, but may vary with respect to capability (e.g.,the total number of components/peripherals that can be supported, thetotal number of communication lanes that can be supported, theconfiguration of lanes, etc.),

As do many technologies, PCI Express is evolving from one generation toa next generation (Gen1 to Gen2) and there is ongoing development forfuture generations (Gen3) yet to be implemented. The PGI Expressspecification mandates that Gen2 components be compatible with Genscomponents. In part, this means that Gen2 components and links (eachlink has one or more lanes) need to be able to operate at a Gen2 datarate (5.0 Gbps) and at a Gen1 data rate (2.5 Gbps). Providing efficientsolutions to the backwards compatibility requirements of PGI Express orother communication architectures is desirable.

BRIEF DESCRIPTION OF THE DRAWINGS

For a detailed description of exemplary embodiments of the invention,reference will now be made to the accompanying drawings in which:

FIG. 1 shows an electronic device in accordance with an embodiment ofthe disclosure:

FIG. 2 shows a serial communication link controller in accordance withan embodiment of the disclosure;

FIG. 3 shows clock divider logic in accordance with an embodiment of thedisclosure;

FIG. 4 shows lock selection logic in accordance with an embodiment ofthe disclosure; and

FIG. 5 shows a method and with an embodiment of the disclosure.

NOTATION AND NOMENCLATURE

Certain terms are used throughout the following description and claimsto refer to particular system components. As one skilled in the art willappreciate, computer companies may refer to a component by differentnames. This document does not intend to distinguish between componentsthat differ in name but not function. In the following discussion and inthe claims, the terms “including” and “comprising” are used in anopen-ended fashion, and thus should be interpreted to mean “including,but not limited to, . . . .” Also, the term “couple” or “couples” isintended to mean either an indirect, direct, optical or wirelesselectrical connection. Thus, if a first device couples to a seconddevice, that connection may be through a direct electrical connection,through an indirect electrical connection via other devices andconnections, through an optical electrical connection, or through awireless electrical connection.

DETAILED DESCRIPTION

The following discussion is directed to various embodiments of theinvention. Although one or more of these embodiments may be preferred,the embodiments disclosed should not be interpreted, or otherwise used,as limiting the scope of the disclosure, including the claims. Inaddition, one skilled in the art will understand that the followingdescription has broad application, and the discussion of any embodimentis meant only to be exemplary of that embodiment, and not intended tointimate that the scope of the disclosure, including the claims, islimited to that embodiment.

Embodiments of the disclosure provide a mechanism for multi-clockgeneration, alignment, distribution, selection, and use, in accordancewith at least some embodiments, the mechanism is applied to a PCIExpress link controller chip. However, at least some componentsimplemented for the multi-clock generation, alignment, distribution, andselection disclosed herein, may alternatively be provided external tothe PCI Express link controller chip. Further, the mechanism describedherein could be applied to other communication protocols (besides PCIExpress) that would benefit from multi-clock generation, alignment,distribution, and selection. As an example, communication protocols thatmandate backwards compatibility, where different clock signals are usedfor the previous generation and the next generation, could benefit fromthe disclosed multi-clock solution.

FIG. 1 shows an embodiment of an electronic device 102 in accordancewith the disclosure. The electronic device 102 is representative of adesktop computer, a laptop computer, a server, a smart phone, a personaldigital assistant (PDA), or other electronic devices that are now knownor later developed. As shown, the electronic device 102 comprises atleast one central processor unit (CPU) 104, which may correspond to atleast one of a variety of semiconductor devices such as microprocessors,microcontrollers, main processing units (MPUs), digital signalprocessors (DSPs), advanced reduced instruction set computing (RISC)machines, ARM processors, application specific integrated circuits(ASICs), field programmable gate arrays (FPGAs) or other processingdevices. The CPU 104 performs a set of predetermined operations based ondata/instructions stored in or accessible to the CPU 104. In at leastsome embodiments, the CPU 104 couples to a memory 106 that storesdata/instructions for use by the CPU 104.

The CPU 104 also couples to a serial communication link controller 110,which provides a communication interface for various internal components112 and/or external components 114. For example, the serialcommunication link controller 110 may enable the internal components 112and/or the external components 114 to communicate with each other inaccordance with a predetermined communication protocol. The serialcommunication link controller 110 also may provide a protocol conversionfunction that enables the internal components 112 and/or the externalcomponents 114 to communicate with the CPU 102 or other host systemcomponents.

In accordance with some embodiments, the serial communication linkcontroller 110 represents PCI Express 2.0 control logic or a PCI Express2.0 chipset. In such case, the serial communication link controller 110interconnects/manages a plurality of PCI Express communication lanes foruse by the internal components 112 and/or the external components 114.The PCI Express standard currently defines a generation 1.0 (Gen1) datarate of 2.5 Gbps and a generation 2.0 (Gen2) data rate of 5.0 Gbps, ThePCI Express standard also mandates that any Gen2 link (having one ormore lanes) must also support Gen1 operations, In accordance withembodiments, the numerous communication lanes in a PCI Expressimplementation may be combined in different ways to form a plurality oflinks having different bandwidths.

As shown, the serial communication link controller 110 receives or hasaccess to a single clock source (“Input Clk”). As will later bedescribed in greater detail, this clock source is used to generate atleast two separate clock signals (e.g., a Gen1 clock signal and a Gen2clock signal). A fixed phase relationship between the two separate clocksignals is maintained. Also, a low-skew clock distribution and selectionscheme is implemented that enables the same logic to be used for dataflow, regardless of whether a communication link operates with a firstclock signal (e.g., a Gen2 clock) or a second clock signal (e.g., a Gen1clock) and regardless of whether changes are made in the aggregation ofcommunication lanes into links or “bundles.” In accordance with at eastsome embodiments, the first clock signal is a buffered version of InputClk and the second clock signal is a buffered and divided version ofInput Clk. The phase alignment of the first clock signal with respect tothe second clock signal is maintained even if communication laneassignments and/or link speeds change.

FIG. 2 shows an embodiment of the serial communication link controller110 of FIG. 1 in accordance with the disclosure. As shown, the serialcommunication link controller 110 comprises a plurality of bundles210A-210N. Each of the bundles 210A-210N is an aggregation of at leastone communication lane and associated physical layer logic. Inaccordance with at least some embodiments, each of the bundles 210A-210Nis able to dynamically select one of multiple clock signals to supportcommunications or other functions. For example, in a PCI Expressembodiment, each of the bundles 210A-210N is able to dynamically selecta Gen1 clock signal or a Gen2 clock signal. Alternatively, once Gen3 isimplemented, each of the bundles 210A-210N is able to dynamically selecta Gen1 clock signal, a Gen2 clock signal, or a Gen3 clock signal. Foreach of the bundles 210A-210N, the selected clock signal may be providedto respective link control logic 230A-230N, where each link controllogic 230A-230N supports communication functions (e.g., decoding, symbolalignment, or other functions) for its respective bundle.

As shown, the first and second clocks are distributed from a clockdistribution hub 202 having a clock divider 204 and buffers 20 b and208. In accordance with some embodiments, the clock divider 204 receivesan input differential clock and generates two separate outputdifferential clocks. One of the output differential clocks passesthrough the buffer 206 and the other passes through the buffer 208. Insome embodiments, one output differential clock may have the samefrequency as the input differential clock while the other has half thefrequency of the input differential clock. The clock divider 204 mayadditionally or alternatively support other clock frequencies based onthe input clock (e.g., by dividing by a value greater than 2). Thiswould be the case, for example, if the clock divider 204 is configuredto output a Gen3 clock signal, a Gen2 clock signal and a Gen1 clocksignal. Once the division and buffering steps have occurred, the clockdistribution hub 202 outputs the resulting clock signals fordistribution to each of the bundles 210A-210N.

Each bundle 210A-210N respectively comprises clock selection logic220A-220N that receives the resulting clock signals and that selects oneof the resulting clock signals for use with bundle communications. Theselection process may be based on a separate control signal (“select”)received by each clock selection logic 220A-220N. In accordance with atleast some embodiments, each clock selection logic 220A-220N is able todynamically switch between the received clock signals. Also, in someembodiments, the bundles 210A-210N are subject to dynamic re-bundling,which changes the number of lanes assigned to each bundle. Further, insome embodiments, different bundles may have multiple copies of theclock selection logic 220 so as to select multiple clock signal copiesfor use by the given bundle. In other words, the number of clock signalcopies used by each bundle 210A-210N may vary depending on the number ofcommunication lanes assigned or other reasons.

FIG. 3 shows an embodiment of clock divider logic 300 in accordance withthe disclosure. The clock divider logic 300 would be repeated for eachclock signal to be output from the clock distribution hub 202. Thus, insome PCI Express embodiments, the clock divider 204 has two copies ofthe clock divider logic 300 (one copy of the clock divider logic 300 isused to output a Gen1 differential clock to the buffer 206 and anothercopy is used to output a Gen2 differential clock to the buffer 208).Alternatively, the clock divider 204 could have additional copies of theclock divider logic 300 (e.g., if Gen3 is supported). An example ofgenerating a Gen1 differential clock and a Gen2 differential clock usingcopies of the clock divider logic 300 will now be given.

To generate the Gen2 differential clock, the input A is tied to a supplyvoltage (VDD) and the input B is tied to ground (GND). As shown, theinput A is provided to an inverter 310A, which outputs NA (“not” A). Asused herein, “not” refers the logical opposite (logical “highs” and“lows”). NA then passes through inverter 312A, which outputs A_(Buf) (abuffered version of A). Meanwhile, A passes through, inverter 314A,which outputs NA_(Buf) (“not” A_(Buf)). Similarly, the input B isprovided to an inverter 310B, which outputs NB (“not” B). NB then passesthrough inverter 312B, which outputs B_(Buf) (a buffered version of B).Meanwhile, B passes through inverter 314B, which outputs NB_(Buf) (“not”B_(Buf)).

In the clock divider logic 300, pulse-based signals (PCKA, NPCKA) areprovided by inputting a clock signal (CKA) to link drive pulse logic302A having a pulse generator 304A. As shown, an enable signal (“EnableA”) is passed through a buffer 308A and on to the pulse generator 304Ato selectively enable pulse generation. The output of the pulsegenerator 304A is a pulsed version of CKA (“PCKA”). For example, PCKAmay comprise a pulse for each rising clock edge of CKA. PCKA is providedto an inverter 306A, which outputs NPCKA (“not” PCKA).

Similarly, additional pulse-based signals (PCKB, NPCKB) are provided byinputting a clock signal (CKB) to link drive pulse logic 302B having apulse generator 304B. As shown, an enable signal (“Enable B”) is passedthrough a buffer 308B and on to the pulse generator 304B to selectivelyenable pulse generation. The output of the pulse generator 304B is apulsed version of CKB (“PCKB”). For example, PCKB may comprise a pulsefor each rising clock edge of CKB. PCKB is provided to an inverter 306B,which outputs NPCKB (“not” PCKB). In accordance with some embodiments,CKA and CKB are obtained from a differential Gen2 clock input to theclock divider 204. In alternative embodiments, CKA and CKB could be aGen3 clock input or another highest speed clock signal in aconfiguration.

As shown, the clock divider logic 300 also comprises pass signal logic320 and 322 that corresponds to a pass signal gate topology. The passsignal logic 320 receives A_(Buf) and B_(Buf) as inputs and passes oneof these signals based on the pulsed signals (PCKA, NPCKA, PCKB, NPCKB).Similarly, the pass signal logic 322 receives NA_(Buf) and NB_(Buf) asinputs and passes one of these signals based on the pulsed signals(PCKA, NPCKA, PCKB, NPCKB). The pass signal logic 320 provides itsoutput (NOUTN) to an inverter 326A, which outputs OUTN from the clockdivider logic 300. Meanwhile, the pass signal logic 322 provides itsoutput (NOUTP) to an inverter 326B, which outputs OUTB from the clockdivider logic 300. As shown in FIG. 3, cross-coupling differentialinverters 324 are placed between the outputs of the pass signal logic320 and 322 to ensure a differential clock output. In the exampleprovided, the OUTN and OUTP from the clock divider logic 300 maycorrespond to a Gen2 differential clock that is output from the clockdivider 204 of FIG. 2 and is provided to the buffer 208.

As previously mentioned, another copy of the clock divider logic 300 canbe used to output a Gen1 differential clock to the buffer 206. In suchcase, the input A is tied to supply voltage (VDD) and the input B istied to ground (GND), but the polarity of A and B are switched everyother clock cycle (assuming the clock cycles of a Gen2 input clock).

Using copies of the clock divider logic 300, the clock divider 204 isable to receive a single input clock and create at least two separateclock signals from the input clock, where one of the clock signals isone half the frequency of the other clock signal. In at least someembodiments, the input clock corresponds to the output of a transmitphase-locked loop (PLL) that is part of a PCI Express 2.0 chipset. Theclock divider logic 300 edge-aligns the two separate clock signals towithin a narrow (or tight) tolerance. For example, in some embodiments,the falling edge of one of the clock signals never precedes nor trailsthe falling edge of the other clock signal by more than 10 picoseconds.These edge-aligned clock signals are distributed to the communicationlink bundles, where one of the clock signals is selected for each givencommunication lane based on the each lane's bundle assignment (sometimesreferred to as “bifurcation”) and data-rate characteristics.

The combination of tightly aligned clock signals and a low-skewdistribution and selection scheme enables the distribution of both clocksignals to the entire PCI Express control logic (i.e., to every pointthat uses the clock signals) with a low clock skew (e.g., 100picoseconds). In accordance with some embodiments, the edge-alignment,distribution, and selection scheme enable a single instantiation of allthe PCI Express control logic. Also, pre-existing logic signals can beused to select which of the at least two clock signals output from theclock distribution hub 202 is used for each communication link bundle.

By creating separate clock signals having a precise and invariantedge-alignment to each other, switching between the two clock signals(on transition from one data rate to the other) can occur withoutcreating glitches (small pulses that can cause electrical malfunctions).In accordance with at least some embodiments, switching between the twoclock signals occurs when the clock signals have the same voltage level(e.g., both are “high”).

FIG. 4 shows an embodiment of the clock selection logic 220 of FIG. 2 inaccordance with the disclosure. As shown, the clock selection logic 220may comprise a multiplexer 412 that receives multiple clock signals(“clk1” and “clk2”) from the clock distribution hub 202. In alternativeembodiments, the multiplexer 412 selects from three or more clocksignals having different clock rates. In at mast some embodiments, clk1has a higher frequency that clk2 (e.g., clk1 may correspond to a Gen2clock and clk2 may correspond to a Gen1 clock).

The control signal (“sel”) for the multiplexer propagates through a flipflop chain that includes flip flop 406 in series with flip flop 410.This flip flop chain may be referred to as “glitch control logic.” In atleast some embodiments, the flip flop 406 corresponds to a “slow clockflip flop” because it is docked by clk2 and the flip flop 410corresponds to a “fast clock flip flop” because it is clocked by clk1.In operation, the output state of the flip flops 406 and 410 change onthe rising edge of their respective input clocks. Accordingly, the flipflop 406 propagates any changes to a corresponding control signal(“select”) on the rising edge of clk2 (the slower clock signal). Theoutput of flip flop 406 is buffered by buffer 408 and is then input toflip flop 410, which propagates any changes to the control signal on therising edge of clk1 (the faster clock signal). Thus, any changes to thecontrol signal of the multiplexer 412 will only be received by themultiplexer 412 when clk1 and clk2 are at the same voltage level (alogical “high”). In this manner, glitches due to switching between clk1and clk2 are prevented.

FIG. 5 shows a method 500 in accordance with embodiments of hedisclosure. The method 500 comprises receiving an input clock (block502). At block 504, the input clock is divided and low-skew, bufferedversions of the input clock and the divided input clock are output. Atblock 506, the low-skew, buffered versions of the input clock and thedivided input clock are provided to each of a plurality of communicationlink bundles. The method 500 further comprises dynamically selecting oneof the low-skew, buffered versions of the input clock and the dividedinput clock for each bundle (block 510). If the bundles are modified(determination block 508), the method 500 returns to block 510. Themethod 500 may alternatively include additional or fewer steps.

For example, in at least some embodiments, the method 500 may comprisemaintaining an edge-alignment of the first and second clock signal usinga pass signal gate topology. Also, the method 500 may comprisedynamically selecting one of the low-skew, buffered versions of theinput clock and the divided input clock for each bundle by causingswitches between the first and second clock signals to occur when boththe first and second clock signals are asserted.

The above discussion is meant to be illustrative of the principles andvarious embodiments of the present invention. Numerous variations andmodifications will become apparent to those skilled in the art once theabove disclosure is fully appreciated. It is intended that the followingclaims be interpreted to embrace all such variations and modifications.

What is claimed is:
 1. An electronic device, comprising: a plurality ofcommunication link bundles that provide communication between aprocessor of the electronic device and other components of theelectronic device, wherein at least one of the communication linkbundles comprises a plurality of communication lanes; and a plurality ofclock selection circuits, one for each communication link bundle, eachone dynamically selecting a clock signal out of multiple clock signalsfor use by its respective communication link bundle.
 2. The electronicdevice of claim 1, wherein the plurality of communication link bundlesare compatible with a PCI Express communication protocol.
 3. Theelectronic device of claim 1, further comprising a clock distributionhub that receives an input clock and outputs the multiple clock signals.4. The electronic device of claim 3, wherein the multiple clock signalsinclude a first clock signal that is a buffered version of the inputclock and a second clock signal that is a buffered and divided versionof the input clock.
 5. The electronic device of claim 3, wherein themultiple clock signals each have a different data rate, and wherein theclock distribution hub maintains phase alignment between the multipleclock signals.
 6. The electronic device of claim 3, wherein one of themultiple clock signals has a PCI Express Gen 1 data rate and another ofthe multiple clock signals has a PCI Express Gen 2 data rate.
 7. Theelectronic device of claim 1, wherein a serial communication linkcontroller is capable of dynamically re-bundling the communication linkbundles to change the number of communication lanes associated with eachcommunication link bundle.
 8. The electronic device of claim 7, whereina clock distribution hub maintains phase alignment between the multipleclock signals even when the dynamically re-bundling occurs.
 9. Theelectronic device of claim 1, wherein each clock selection circuitincludes at least one multiplexer that receives the multiple clocksignals and selects the clock signal for its respective communicationlink bundle.
 10. A serial communication link controller of an electronicdevice, comprising: a plurality of communication link bundles thatprovide communication between a processor of the electronic device andother components of the electronic device, wherein at least one of thecommunication link bundles comprises a plurality of communication lanes;and a plurality of clock selection circuits, at leash one for eachcommunication link bundle, each one dynamically selecting a clock signalout of multiple clock signals for use by at least part of its respectivecommunication link bundle.
 11. The serial communication link controllerof claim 10, further comprising a clock distribution hub that receivesan input clock and outputs the multiple clock signals, wherein themultiple clock signals each have a different data rate, and wherein theclock distribution hub maintains phase alignment between the multipleclock signals.
 12. The serial communication link controller of claim 11,wherein the clock distribution hub includes at least one clock dividerto provide one of the multiple clock signals with a frequency that ishalf the frequency of another one of the multiple clock signals.
 13. Theserial communication link controller of claim 10, wherein at least oneof the communication link bundles has multiple clock selection circuits,each one dynamically selecting a clock signal for part of its respectivecommunication link bundle.
 14. A method, comprising: providing aplurality of communication link bundles that allow for communicationbetween a processor of an electronic device and other components of theelectronic device, wherein at least one of the communication linkbundles comprises a plurality of communication lanes; generatingmultiple clock signals based on an input clock; dynamically selecting,by each of a plurality of clock selection circuits, a clock signal outof multiple clock signals, wherein each clock selection circuit isassociated with one of the communication link bundles; and using, byeach communication link bundle, the clock signal selected for theparticular communication link bundle.
 15. The method of claim 14,wherein one of the multiple clock signals has a data rate of 5.0 Gbpsand another of the multiple clock signals has a data rate of 2.5 Gbps.